In current semiconductor technology, there is an ongoing trend to increase the performance of a semiconductor chip by shifting from a two-dimensional (2D) chip format to a three-dimensional (3D) chip format. This requires a wafer-to-wafer (or even a chip-to-chip) vertical interconnect.
Vertical interconnects are preferably made by way of a reduced sized solder bump area array interconnect scheme, which is often called a flip-chip solder connection or C4. However, the present lead based C4s are themselves a source of alpha radiation and they typically interfere with the need for a radiation-free interconnect material. Alpha radiation is undesirable since it may introduce soft errors into the semiconductor device. It is noted that not all semiconductor designs are affected by alpha-radiation.
Furthermore, the new lead free C4s that are presently being considered consist mainly of tin (Sn), which itself may be a source of alpha radiation. Hence, these new C4s do not assure the elimination of the alpha radiation issue.
Alternative interconnection can be achieved with a metal stud-to-pad approach. This method, which is described, for example, in U.S. Pat. No. 6,444,560 to Pogge et al., is termed the T&J (transfer and join) approach. A typical T&J interconnect consists of a metal stud (preferably copper, Cu) coated with an alloying metal (typically Sn). The Sn assists the alloying of the metal stud to an opposing metal pad (typically Cu as well). As with the previously mentioned C4 technology, the T&J approach includes Sn which may also be an alpha radiation source.
To accommodate the ability to attach a second semiconductor chip to a first semiconductor chip dictates the need for a vertical through via in the second chip so that there is an electrical path from the first chip through the second chip and to a supporting substrate that is located beneath the second chip. Through via processing has been exercised by a number of semiconductor manufacturers. However, an efficient through via fabrication and through via metal filling has remained a challenge. There is a concern to assure the creation of a smooth vertical through via, rather than some form of corrugated surfaced through via. The latter may initiate metal voids within the metal filled through via which can lead to unacceptable conductivity variations.
In view of the above, there is a need for providing an alternative method for fabricating an improved metal filled through via that overcomes the above mentioned through via concerns as well as avoiding alpha radiation source issues generated by C4s or possible Sn based alloying T&J interconnects.